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1 HD66705U (low-power dot-matrix liquid crystal display controller/driver) ade-207-305(z) '99.9 rev. 0.0 description the HD66705U dot-matrix liquid crystal display controller and driver lsi displays alphanumerics, katakana, hiragana, and symbols. it can be configured to drive a dot-matrix liquid crystal display under the control of a clock-synchronized serial, or a 4- or 8-bit microprocessor. a single HD66705U is capable of displaying a maximum of two 12-character lines, 40 segments, and 10 annunciators. the HD66705U incorporates all the functions required for driving a dot-matrix liquid crystal display such as display ram, character generator, and liquid crystal drivers, and a booster for lcd power supply. the HD66705U provides various functions to reduce the power consumption of an lcd system such as low-voltage operation of 2.4v or less, a booster for generating a maximum of triple lcd drive voltage from the supplied voltage, and voltage-followers for decreasing the direct current flow in the lcd drive bleeder-resistors. combining these hardware functions with software functions such as standby and sleep modes allows a fine power control. the HD66705U, with the above functions, is suitable for any portable battery-driven product requiring long-term driving capabilities and small size. features 5 8-dot matrix lcd drive two 12-character lines, 40 segments, and 10 annunciators low-power operation support: ? 2.4 to 5.5v (low voltage) ? double or triple booster for liquid crystal drive voltage ? electron volume function and voltage-followers for decreasing the direct current flow in the lcd drive bleeder-resistors ? standby mode and sleep mode ? displays up to 10 static annunciators without lcd power supply clock-synchronized serial interface; 4- or 8-bit parallel bus interface 60 8-bit display data ram (60 characters max) 9,600-bit character generator rom
HD66705U 2 240 characters (5 8 dots) 32 5-bit character generator ram ? 4 characters (5 8 dots) 8 5-bit segment ram ? 40 segment-icons and marks max 60-segment 34-common liquid crystal display driver programmable display sizes and duty ratios (see list1) vertical smooth scroll double-height display wide range of instruction functions: ? display clear, display on/off, icon and mark control, character blink, white-black inverting blinking cursor, icon and mark blink, cursor home, cursor on/off, white-black inverting raster-row hardware reset internal oscillation with an external resistor wide range of lcd drive voltages ? 3.0v to 9.0v slim chip with au-bump (for cog) and tape carrier package (tcp) list 1 programmable display sizes and duty ratios and current consumption display size duty ratio oscillation frequency current consumption (normal) (sleep) (standby) multi-plexed-drive segments static-drive annunciators 1 line 12 characters 1/10 40 khz 8 m a6 m a 0.1 m a40 10 2 lines 12 characters 1/18 85 khz 15 m a 12 m a 0.1 m a40 10 note: current consumption excludes that for lcd power supply source; v cc = 3v. list 2 ordering information type name external dimensin operation voltage internal font HD66705Ua03ta0 tcp 2.4v to 5.5v japanese and european fonts hcd66705ua03bp au-bumped chip
HD66705U 3 lcd-ii family comparison item lcd-ii (hd44780u) hd66702r hd66710 hd66712u power supply voltage 2.7v to 5.5v 5v 10% (standard) 2.7v to 5.5v (low voltage) 2.7v to 5.5v 2.7v to 5.5v liquid crystal drive voltage 3.0 to 11.0v 3.0v to 8.3v 3.0 to 13.0v 2.7 to 11.0v maximum display - characters per chip 8 characters 2 lines 20 characters 2 lines 16 characters 2 lines/ 8 characters 4 lines 24 characters 2 lines/ 12 characters 4 lines segment display none none 40 60 (extended to 80) display duty ratio 1/8, 1/11, and 1/16 1/8, 1/11, and 1/16 1/17 and 1/33 1/17 and 1/33 cgrom 9,920 bits (208 5- -8 dot characters and 32 5- -10 dot characters) 7,200 bits (160 5- -7 dot characters and 32 5- -10 dot characters) 9,600 bits (240 5- -8 dot characters) 9,600 bits (240 5- -8 dot characters) cgram 64 bytes 64 bytes 64 bytes 64 bytes ddram 80 bytes 80 bytes 80 bytes 80 bytes segram none none 8 bytes 16 bytes segment signals 40 100 40 60 common signals 16 16 33 34 liquid crystal drive waveform ab b b clock source external resistor or external clock external resistor or external clock external resistor or external clock external resistor or external clock rf oscillation frequency 270 khz 30% 320 khz 30% 270 khz 30% 270 khz 30% liquid crystal voltage booster circuit none none double or triple booster circuit double or triple booster circuit liquid crystal drive operational amplifier none none none none bleeder-resistor for liquid crystal drive external external external external liquid crystal contrast adjuster none none none none key scan circuit none none none none extension driver control signal independent control signal independent control signal used in common with a driver output pin independent control signal reset function internal reset circuit internal reset circuit internal reset circuit internal reset circuit or reset input horizontal smooth scroll impossible impossible dot unit dot unit and line unit vertical smooth scroll impossible impossible impossible impossible number of displayed lines 1 or 2 1 or 2 1, 2, or 4 1, 2, or 4 low power control none none low power mode low power mode bus interface 4 or 8 bits 4 or 8 bits 4 or 8 bits serial, 4, or 8 bits package 80-pin qfp1420 80-pin tqfp1414 80-pin bare chip 144-pin fqfp2020 144-pin bare chip 100-pin qfp1420 100-pin tqfp1414 100-pin bare chip 128-pin tcp 128-pin bare chip
HD66705U 4 lcd-ii family comparison (cont) item hd66720 HD66705U hd66717 hd66727 power supply voltage 2.7v to 5.5v 2.4v to 5.5v 2.4v to 5.5v 2.4v to 5.5v liquid crystal drive voltage 3.0 to 11.0v 3.0 to 9.0v 3.0 to 13.0v 3.0 to 13.0v maximum display characters per chip 10 characters 1 line/ 8 characters 2 lines 12 characters 1 line/2 lines 12 characters 1 line/2 lines/ 3 lines/4 lines 12 characters 1 line/2 lines/ 3 lines/4 lines segment display 42 (extended to 80) 40 and 10 annunciators 40 and 10 annunciators 40 and 12 annunciators display duty ratio 1/9 and 1/17 1/10, 1/18 1/10, 1/18, 1/26, and 1/34 1/10, 1/18, 1/26, and 1/34 cgrom 9,600 bits (240 5- -8 dot characters) 9,600 bits (240 5- -8 dot characters) 9,600 bits (240 5- -8 dot characters) 11,520 bits (240 6- -8 dot characters) cgram 64 bytes 32 bytes 32 bytes 32 bytes ddram 40 bytes 60 bytes 60 bytes 60 bytes segram 16 bytes 8 bytes 8 bytes 8 bytes segment signals 42 60 60 60 common signals 17 18 34 34 liquid crystal drive waveform bb b b clock source external resistor or external clock external resistor or external clock external resistor or external clock external resistor or external clock rf oscillation frequency 160 khz 30% 1-line: 40 khz 30% 2-line: 85 khz 30% 1-line: 40 khz 30% 2-line: 85 khz 30% 3-line: 120 khz 30% 4-line: 160 khz 30% 1-line: 40 khz 30% 2-line: 85 khz 30% 3-line: 120 khz 30% 4-line: 160 khz 30% liquid crystal voltage booster circuit double or triple booster circuit double or triple booster circuit double or triple booster circuit double or triple booster circuit liquid crystal drive operational amplifier none built-in for each v1 to v5 built-in for each v1 to v5 built-in for each v1 to v5 bleeder-resistor for liquid crystal drive external internal 1/4 bias and 1/5 bias resistors internal 1/4 and 1/6 bias resistors internal 1/4 and 1/6 bias resistors liquid crystal contrast adjuster none incorporated incorporated incorporated key scan circuit 5 6 = 30 keys none none 4 8 = 32 keys extension driver control signal independent control signal none none none reset function internal reset circuit or reset input reset input reset input reset input horizontal smooth scroll dot unit and line unit impossible impossible impossible vertical smooth scroll impossible dot (raster-row) unit dot (raster-row) unit dot (raster-row) unit number of displayed lines 1 or 2 1 or 2 1, 2, 3, or 4 1, 2, 3, or 4 low power control low power mode and sleep mode standby mode and sleep mode standby mode and sleep mode standby mode and sleep mode bus interface serial serial, 4, or 8 bits i 2 c, serial, 4, or 8 bits i 2 c or clock- synchronized serial package 100-pin qfp1420 100-pin tqfp1414 100-pin bare chip slim chip with bumps tcp slim chip slim chip with bumps tcp slim chip slim chip with bumps tcp
HD66705U 5 HD66705U block diagram input/ output buffer data register (dr) instruction register (ir) address counter timing generator display data ram (ddram) 60 8 bits character generator ram (cgram ) 32 bytes character generator rom (cgrom) 9,600 bits parallel/serial converter 18-bit shift register common signal driver lcd drive voltage selector cursor and blink controller cpg instruction decoder rs/cs* rw/sda e/scl db7?b6 db5/id5 ?b0/id0 v cc gnd com1 com16 seg1 seg60 osc1 osc2 8 7 8 5 7 8 7 7 8 8 5 5 vci booster c1 5 3 segment ram (segram) 8 bytes im1/0 reset* c2 + + v3 v2 + + v5out2 v5out3 annunciator driver aseg1? aseg10 acom v ee coms1/2 exm rrrrr vr test sft v1out v2out v3out v4out v5out opoff agnd system interface ?clock- synchro- nized serial ?4 bits ?8 bits busy flag 60-bit shift register 60-bit latch circuit segment signal driver +
HD66705U 6 HD66705U pin arrangement dummy24 dummy23 dummy22 dummy21 dummy20 seg60 seg59 seg58 seg57 seg56 seg55 seg54 seg53 seg52 seg51 seg50 seg49 seg48 seg47 seg46 seg45 seg44 seg43 seg42 seg41 seg40 seg39 seg38 seg37 seg36 seg35 seg34 seg33 seg32 seg31 seg30 seg29 seg28 seg27 seg26 seg25 seg24 seg23 seg22 seg21 seg20 seg19 seg18 seg17 seg16 seg15 seg14 seg13 seg12 seg11 seg10 seg9 seg8 seg7 seg6 seg5 seg4 seg3 seg2 seg1 aseg10 aseg9 aseg8 aseg7 aseg6 aseg5 aseg4 aseg3 aseg2 aseg1 acom1 dummy19 v1out v2out v3out v4out v5out vrefp vref vrefm v2 v3 v ee v ee v5out3 v5out3 v5out2 v5out2 c1 c1 c1 c2 c2 c2 v ci v ci db4/id4 db5/id5 db6 db7 gnd gnd gnd gnd agnd agnd dummy 1 reset * rs/cs * e/scl rw/sda db0/id0 db1/id1 db2/id2 db3/id3 gnd gnd v cc v cc osc2 osc1 exm sft im1 im0 opoff test HD66705U (top view) y x chip size coordinate origin au-bump size : 9.69 2.73 mm : pad center : chip center : 70 m 70 m v cc v cc coms2 com1 com2 com3 com4 com5 com6 com7 com8 com9 com10 com11 com12 com13 com14 com15 com16 coms1 dummy18 dummy17 dummy16 dummy15 dummy14 dummy13 dummy12 dummy11 dummy10 dummy9 dummy8 dummy7 dummy6 dummy5 dummy4 dummy3 dummy2
HD66705U 7 HD66705U pad coordinates pad name x y pad name x y pad name x y pad name x y v cc ?888 ?171 db3/id3 2843 ?122 seg5 2586 1125 seg50 ?684 1125 v cc ?771 ?171 db4/id4 3047 ?122 seg6 2469 1125 seg51 ?801 1125 v1out ?516 ?100 db5/id5 3251 ?122 seg7 2352 1125 seg52 ?918 1125 v2out ?403 ?100 db6 3455 ?122 seg8 2235 1125 seg53 ?035 1125 v3out ?290 ?100 db7 3659 ?122 seg9 2118 1125 seg54 ?152 1125 v4out ?176 ?100 gnd 3865 ?130 seg10 2001 1125 seg55 ?270 1125 v5out ?063 ?100 gnd 3978 ?130 seg11 1884 1125 seg56 ?387 1125 vrefp ?950 ?100 gnd 4119 ?130 seg12 1767 1125 seg57 ?504 1125 vref ?837 ?100 gnd 4233 1130 seg13 1649 1125 seg58 ?621 1125 vrefm ?723 ?100 agnd 4386 ?130 seg14 1532 1125 seg59 ?738 1125 v2 ?610 ?100 agnd 4500 ?130 seg15 1415 1125 seg60 ?855 1125 v3 ?496 ?100 dummy1 4686 ?171 seg16 1298 1125 dummy20 ?972 1125 v ee ?382 ?099 dummy2 4686 ?57 seg17 1181 1125 dummy21 ?089 1125 v ee ?269 ?099 dummy3 4686 ?40 seg18 1064 1125 dummy22 ?207 1125 v5out3 ?122 ?099 dummy4 4686 ?23 seg19 947 1125 dummy23 ?324 1125 v5out3 ?008 ?099 dummy5 4686 ?06 seg20 830 1125 dummy24 ?605 1125 v5out2 ?838 ?099 dummy6 4686 ?89 seg21 712 1125 coms2 ?605 917 v5out2 ?725 ?099 dummy7 4686 ?72 seg22 595 1125 com1 ?605 800 c1 ?584 ?099 dummy8 4686 ?54 seg23 478 1125 com2 ?605 682 c1 ?470 ?099 dummy9 4686 ?37 seg24 361 1125 com3 ?605 565 c1 ?357 ?099 dummy10 4686 ?0 seg25 244 1125 com4 ?605 448 c2 ?214 ?099 dummy11 4686 97 seg26 127 1125 com5 ?605 331 c2 ?101 ?099 dummy12 4686 214 seg27 10 1125 com6 ?605 214 c2 ?87 ?099 dummy13 4686 331 seg28 ?07 1125 com7 ?605 97 vci ?45 ?099 dummy14 4686 448 seg29 ?24 1125 com8 ?605 ?0 vci ?31 ?099 dummy15 4686 565 seg30 ?42 1125 com9 ?605 ?37 gnd ?89 ?099 dummy16 4686 682 seg31 ?59 1125 com10 ?605 ?54 gnd ?75 ?099 dummy17 4686 800 seg32 ?76 1125 com11 ?605 ?72 v cc ?38 ?099 dummy18 4686 917 seg33 ?93 1125 com12 ?605 ?89 v cc ?24 ?099 dummy19 4686 1125 seg34 ?10 1125 com13 ?605 ?06 osc2 ?8 ?122 acom1 4460 1121 seg35 ?27 1125 com14 ?605 ?23 osc1 108 ?122 aseg1 4343 1121 seg36 ?044 1125 com15 ?605 ?40 exm 300 ?122 aseg2 4226 1121 seg37 ?161 1125 com16 ?605 ?57 sft 492 ?122 aseg3 4109 1121 seg38 ?279 1125 coms1 ?605 ?171 im1 684 ?122 aseg4 3992 1121 seg39 ?396 1125 (target) ?530 1135 im0 876 ?122 aseg5 3875 1121 seg40 ?513 1125 (target) ?530 ?183 opoff 1068 ?122 aseg6 3758 1121 seg41 ?630 1125 (target) 4606 ?183 test 1260 ?122 aseg7 3640 1121 seg42 ?747 1125 (target) 4606 1135 reset 1452 ?122 aseg8 3523 1121 seg43 ?864 1125 (target) ?530 1090 rs/cs 1644 ?122 aseg9 3406 1121 seg44 ?981 1125 (target) 4606 1090 e/scl 1836 ?122 aseg10 3289 1121 seg45 ?098 1125 rw/sda 2031 ?122 seg1 3055 1125 seg46 ?216 1125 db0/id0 2231 ?122 seg2 2938 1125 seg47 ?333 1125 db1/id1 2435 ?122 seg3 2821 1125 seg48 ?450 1125 db2/id2 2639 ?122 seg4 2704 1125 seg49 ?567 1125
HD66705U 8 tcp dimensions vcc v1out v2out v3out v4out v5out vrefp vref vrefm vee v5out3 v5out2 c1 c2 vci gnd vcc osc2 osc1 exm sft im1 im0 opoff test reset rs/cs e/scl rw/sda db0/id0 db1/id1 db2/id2 db3/id3 db4/id4 db5/id5 db6 db7 gnd agnd 0.24 mm pitch dummy21 dummy20 coms1 com16 seg1 aseg10 aseg1 acoms dummy19 dummy18 dummy3 dummy2 dummy1 i/o, power supply 0.65p (39?) = 24.70 mm note: v2?3 pins are short-circuited internally (1/4 bias lcd driving) lcd driver 0.24p (110?) = 26.16 mm hitachi 0.65mm pitch HD66705U com1 coms2 seg60
HD66705U 9 pin functions table 1 pin functional description signal number of pins i/o device interfaced with function im1, im0 2 i v cc or gnd selects interface mode with the mpu: im1, im0 = gnd, gnd: inhibited (test mode) im1, im0 = gnd, v cc : clock-synchronized serial mode (receive) im1, im0 = v cc , gnd: 8-bit bus mode im1, im0 = v cc , v cc : 4-bit bus mode rs/cs* 1 i mpu selects the HD66705U during clock-synchronized serial mode: low: HD66705U is selected and can be accessed high: HD66705U is not selected and cannot be accessed selects the registers during 4- or 8-bit bus mode: low: instruction register (write); busy flag and address counter (read) high: data registers (write/read) rw/sda 1 i mpu inputs serial (receive) data during clock-synchronized serial mode; selects read/write during 4- or 8-bit bus mode: low: write high: read e/scl 1 i mpu inputs serial clock pulses during clock- synchronized serial mode; enables data read/write during 4- or 8-bit bus mode db7, db6, db5/id5 db4/id4 4 i, i/o mpu inputs the HD66705U 's identification code (id5, id4) during clock-synchronized serial mode;must be fixed to high or low (db7 and db6?. four high-order bidirectional data bus pins for tristate data transfer during 8-bit bus mode. bidirectional data bus pins during 4-bit bus mode. db3/id3, db2/id2, db1/id1, db0/id0, 4 i, i/o mpu inputs the HD66705U 's identification code (id3 to id0) during clock-synchronized serial mode; must be fixed to high or low. four low-order bidirectional data bus pins for tristate data transfer during 8-bit bus mode. must be left disconnected during 4-bit bus mode since they are not used. coms1, coms2 2 o lcd common output signals for segment icon display.
HD66705U 10 table 1 pin functional description (cont) signal number of pins i/o device interfaced with function com1 to com16 16 o lcd common output signals for character display: com1 to com8 for the first line, com9 to com16 for the second line. all the unused pins output deselection waveforms. during sleep mode (slp= 1) or standby mode (stb = 1), all pins output v cc level. seg1 to seg60 60 o lcd segment output signals for segment icon display and character display. during sleep mode (slp = 1) or standby mode (stb = 1), all pins output v cc level. acom 1 o lcd common output signal for annunciator display; can drive display statically between v cc and agnd levels; outputs v cc level while annunciator display is turned off (da = 0). aseg1 to aseg10 10 o lcd segment output signals for annunciator display; can drive display statically between v cc and agnd levels; output v cc level while annunciator display is turned off (da = 0). v2/v3 2 i open or short-circuited v2/v3 are voltage levels for the internal operational amplifiers. these v2 and v3 are short-circuited when 1/4 bias lcd driving. and these v2 and v3 are open when 1/5 bias lcd driving. v1out to v5out 5 i or o used for output from the internal operational amplifiers when they are used (opoff = gnd); when amplifiers' driving capability is insufficient, attach a capacitor to stabilize the output. especially these capacitors for v1out and v4out must be attached. when the amplifiers are not used (opoff = v cc ); v1 to v5 voltages can be supplied to these pins externally. vrefp, vref, 3 i open or short-circuited adjusts the driving capability of the internal operational amplifiers according to the lcd power supply voltage. vrefm lcd power supply voltage (v cc ? ee ) pin settings vref, vrefp, and vrefm v cc ? ee : 3v?v only vref and vrefp shorted v cc ? ee : 4v?v all pins open v cc ? ee : 5v?v all pins shorted v cc ? ee : 7v or more only vref and vrefm shorted v ee 2 power supply gnd power supply for lcd drive v cc ? ee = 9v max. v cc /gnd 10 power supply v cc : +2.4v to +5.5v, gnd (logic): 0v agnd 2 power supply low level power supply for annunciator display; can adjust contrast of annunciators; agnd 3 gnd. osc1/ osc2 2 oscillation resistor/clock for r-c oscillation, connect an external resistor for external clock supply, input clock pulses to osc1.
HD66705U 11 table 1 pin functional description (cont) signal number of pins i/o device interfaced with function vci 2 i power supply inputs a reference voltage and supplies power to the booster; generates the liquid crystal display drive voltage from the operating voltage. v5out2 2 o v ee pin/ booster capacitance voltage input to the vci pin is boosted twice and output. when the voltage is boosted three times, the same capacitance as that of c1?2 should be connected here. v5out3 2 o v ee pin voltage input to the vci pin is boosted three times and output. c1/c2 6 booster capacitance external capacitance should be connected here when using the booster. reset* 1 i reset pin. initializes the lsi when low. must reset after power-on. exm 1 i mpu external alternating signal used for annunciator display during standby mode. if annunciator display is not used, exm must be fixed to v cc or gnd. sft 1 i v cc or gnd selects the seg output pin arrangement: when sft = gnd, seg1 is connected to the far left of the lcd panel and when sft = v cc , seg60 is connected to the far left of the lcd panel opoff 1 i v cc or gnd turns the internal operational amplifier off when opoff = v cc , and turns it on when opoff = gnd. if the amplifier is turned off (opoff = v cc ), v1 to v5 must be supplied to the v1out to v5out pins. test 1 i gnd test pin. must be grounded.
HD66705U 12 block function description system interface the HD66705U has three types of system interfaces: clock-synchronized serial, 4-bit bus, and 8-bit bus. the interface mode is selected by the im1 and im0 pins. the HD66705U has two 8-bit registers: an instruction register (ir) and a data register (dr). the ir stores instruction codes, such as display clear, return home, and display control, and address information for the display data ram (ddram), the character generator ram (cgram), and the segment ram (segram). the ir can only be written to by mpu and cannot be read from. the dr temporarily stores data to be written into ddram, cgram, segram, or annunciator. data written into the dr from the mpu is automatically written into ddram, cgram, segram, or annunciator by an internal operation. the dr is also used for data storage when reading data from ddram, cgram, or segram. when address information is written into the ir, data is read and then stored into the dr from ddram, cgram, or segram by an internal operation. data transfer between the mpu is then completed when the mpu reads the dr. after the read, data in ddram, cgram, or segram at the next address is sent to the dr for the next read from the mpu. these two registers can be selected by the register select (rs) signal in the 4/8-bit bus interface, and by the rs bit in i 2 c bus or clock-synchronized serial interface (table 2). busy flag (bf) when the busy flag is 1, the HD66705U is in the internal operation mode, and the next instruction will not be accepted. when rs = low and r/w = high in 4/8-bit bus mode (table 2), the busy flag is output from db7. the next instruction must be written after ensuring that the busy flag is 0. the busy flag cannot be read in i 2 c bus mode or clock-synchronized serial mode; data must be transferred in appropriate timing considering instruction execution times. address counter (ac) the address counter (ac) assigns addresses to ddram, cgram, or segram. when the address set instruction is written into the ir, the address information is sent from the ir to the ac. selection of ddram, cgram, and segram is also determined concurrently by the instruction. after writing into (reading from) ddram, cgram, or segram, the ac is automatically incremented by 1 (or decremented by 1). the ac contents are then output to db0 to db6 when rs = low and r/w = high in 4/8-bit bus mode (table 2).
HD66705U 13 table 2 register selection rs r/w operation 0 0 ir write as an internal operation (display clear, etc.) 0 1 read busy flag (db7) read and address counter (db0 to db6) (4/8-bit bus interface) 1 0 dr write as an internal operation (dr to ddram, cgram, segram, or annunciator) 1 1 dr read as an internal operation (ddram, cgram, or segram to dr) (4/8-bit bus interface) display data ram (ddram) display data ram (ddram) stores display data represented in 8-bit character codes. its capacity is 60 8 bits, or 60 characters, which is equivalent to an area of 12 characters 5 lines. any number of display lines (lcd drive duty ratio) from 1 to 2 can be selected by software. here, assignment of ddram addresses is the same for all display modes (table 3). the line to be displayed at the top of the display (display-start line) can also be selected by register settings. see table 4. msb example : ddram address 4a address counter (ac) ac 6 ac5 ac4 ac3 ac2 ac1 lsb ac0 1 001010 figure 1 address counter and ddram address table 3 ddram addresses and display positions display line 1st char. 2nd char. 3rd char. 4th char. 5th char. 6th char. 7th char. 8th char. 9th char. 10th char. 11th char. 12th char. 1st 00 01 02 03 04 05 06 07 08 09 0a 0b 2nd 10 11 12 13 14 15 16 17 18 19 1a 1b 3rd 20 21 22 23 24 25 26 27 28 29 2a 2b 4th 30 31 32 33 34 35 36 37 38 39 3a 3b 5th 40 41 42 43 44 45 46 47 48 49 4a 4b note: char. indicates character position.
HD66705U 14 table 4 display-line modes, display-start line, and ddram addresses display-start lines display- line mode duty ratio common pins 1st line (sn = 000) 2nd line (sn = 001) 3rd line (sn = 010) 4th line (sn = 011) 5th line (sn = 100) 1-line (nl = 0) 1/10 com1?om8 00h?bh 10h?bh 20h?bh 30h?bh 40h?bh 2-line (nl = 1) 1/18 com1?om8 com9?om16 00h?bh 10h?bh 10h?bh 20h?bh 20h?bh 30h?bh 30h?bh 40h?bh 40h?bh 00h?bh character generator rom (cgrom) the character generator rom generates 5 8-dot character patterns from 8-bit character codes (table 5). it can generate 240 5 8-dot character patterns. user-defined character patterns are also available using a mask-programmed rom (see the modifying character patterns section.) character generator ram (cgram) the character generator ram of 32 5 bits allows the user to redefine the character patterns for user fonts. in the case of 5 8-dot characters, up to four fonts may be redefined. write the character codes at addresses 00h to 03h into ddram to display the character patterns stored in cgram. segment ram (segram) the segment ram is used to enable control of segments such as an icon and a mark by the user program. segments and characters are driven by a multiplexing drive method. segram has a capacity of 8 5 bits, for controlling the display of a maximum of 40 icons and marks. while coms1 and coms2 outputs are being selected, segram is read and segments (icons and marks) are displayed by a multiplexing drive method (20 segments each during coms1 and coms2 selection). bits in segram corresponding to segments to be displayed are directly set by the mpu, regardless of the contents of ddram and cgram. timing generation circuit the timing generation circuit generates timing signals for the operation of internal circuits such as ddram, cgrom, cgram, and segram. ram read timing for display and internal operation timing by mpu access are generated separately to avoid interfering with each other. therefore, when writing data to ddram, for example, there will be no undesirable interferences, such as flickering, in areas other than the display area.
HD66705U 15 cursor/blink control circuit the cursor/blink (or white-black inversion) control is used to produce a cursor or a flashing area on the display at a position corresponding to the location stored in the address counter (ac). for example (figure 2), when the address counter is 08h, a cursor is displayed at a position corresponding to ddram address (08)h. multiplexing liquid crystal display driver circuit the multiplexing liquid crystal display driver circuit consists of 18 common signal drivers (com1 to com16, coms1, coms2) and 60 segment signal drivers (seg1 to seg60). when the number of lines are selected by a program, the required common signal drivers automatically output drive waveforms, while the other common signal drivers continue to output deselection waveforms. character pattern data is sent serially through a 60-bit shift register and latched when all needed data has arrived. the latched data then enables the segment signal drivers to generate drive waveform outputs. the shift direction of 60-bit data can be selected by the sft pin; select the direction appropriate to the device mounting configuration. when multiplexing drive is not used, or during standby or sleep mode, all common and segment signal drivers output the v cc level, halting display. annunciator driver circuit the static annunciator drivers, which are specially used for displaying icons and marks, consists of 1 common signal driver (acom) and 10 segment signal drivers (aseg1 to aseg10). since this driver circuit operates at the logic operating voltage (v cc ?gnd), the lcd drive power supply circuit is not necessary, and low-power consumption can be achieved. it is suitable for mark indication during system standby because of its drive capability during standby and sleep modes. when multiplexing drive is not used, or during standby or sleep mode, all common and segment signal drivers output the v cc level, halting display. booster the booster doubles or triples a voltage input to the vci pin. with this function, both the internal logic units and lcd drivers can be controlled with a single power supply. oscillator the HD66705U can provide r-c oscillation simply by adding an external oscillation resistor between the osc1 and osc2 pins. the appropriate oscillation frequency for operating voltage, display size, and frame frequency can be obtained by adjusting the external-resistor value. clock pulses can also be supplied externally. since r-c oscillation is halted during standby mode, current consumption can be reduced.
HD66705U 16 v-pin voltage-followers a voltage-follower for each voltage level (v1 to v5) reduces current consumption by the lcd drive power supply circuit. no external resistors are required because of the internal bleeder-resistor, which generates different levels of lcd drive voltage. the voltage-followers can be turned off while multiplexing drive is not being used. contrast-adjuster the contrast-adjuster can adjust lcd contrast by varying lcd drive voltage by software. this function is suitable for selecting appropriate brightness of the lcd or for temperature compensation. cursor position display position ddram address note: the cursor/blink or white-black inversion control is also active when the address counter indicates the cgram or segram. however, it has no effect on the display. 12345678 11 910 12 00 01 02 03 04 05 06 07 0a 08 09 0b figure 2 cursor position and ddram address
HD66705U 17 table 5 relation between character codes and character patterns (rom code: a03) xxxx 0000 xxxx 0001 xxxx 0010 xxxx 0011 xxxx 0100 xxxx 0101 xxxx 0110 xxxx 0111 xxxx 1000 xxxx 1001 xxxx 1010 xxxx 1011 xxxx 1100 xxxx 1101 xxxx 1110 xxxx 1111 lower bits upper bits 0000 0010 0011 0100 0101 0110 0111 1010 1011 1100 1101 1110 1111 1000 1001 0001 cg ram (1) cg ram (2) cg ram (3) cg ram (4) cg ram (1) cg ram (2) cg ram (3) cg ram (4) cg ram (1) cg ram (2) cg ram (3) cg ram (4) cg ram (1) cg ram (2) cg ram (3) cg ram (4)
HD66705U 18 modifying character patterns character pattern development procedure the following operations correspond to the numbers listed in figure 3: 1. determine the correspondence between character codes and character patterns. 2. create a listing indicating the correspondence between eprom addresses and data. 3. program the character patterns into an eprom. 4. send the eprom to hitachi. 5. computer processing of the eprom is performed at hitachi to create a character pattern listing, which is sent to the user. 6. if there are no problems within the character pattern listing, a trial lsi is created at hitachi and samples are sent to the user for evaluation. when it is confirmed by the user that the character patterns are correctly written, mass production of the lsi will proceed at hitachi.
HD66705U 19 determine character patterns create eprom address data listing write eprom eprom ? hitachi computer processing create character pattern listing evaluate character patterns ok? art work sample evaluation ok? masking trial sample no yes no yes m/t 1 3 2 4 5 6 user hitachi mass production start figure 3 character pattern development procedure
HD66705U 20 programming character patterns this section explains the correspondence between addresses and data used to program character patterns in eprom. programming to eprom the HD66705U character generator rom can generate 240 5 8-dot character patterns. table 7 shows correspondence between the eprom address data and the character pattern. handling unused character patterns 1. eprom data outside the character pattern area: this is ignored by the character generator rom for display operation so any data is acceptable. 2. eprom data in cgram area: always fill with zeros. 3. treatment of unused user patterns in the HD66705U eprom: according to the user application, these are handled in either of two ways: a. when unused character patterns are not programmed: if an unused character code is written into ddram, all its dots are lit, because the eprom is filled with 1s after it is erased. b. when unused character patterns are programmed as 0s: nothing is displayed even if unused character codes are written into ddram. (this is equivalent to a space.) table 7 example of correspondence between eprom address data and character pattern (5 8 dots) a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 000 00 1 010 011 100 101 11 0 111 1 000 1 o4 o3 o2 o1 o0 1 0001 1 0001 01 010 0 0100 0 0100 00 1 00 0 0000 character code line position eprom address data lsb msb 0 0 0 0 0 0 0 0 ? a11 0 1011001 notes: 1. eprom addresses a11 to a4 correspond to a character code. 2. eprom addresses a2 to a0 specify the line position of the character pattern. eprom address a3 should be set to 0. 3. eprom data o4 to o0 correspond to character pattern data. 4. areas which are lit (indicated by shading) are stored as 1, and unlit areas as 0. 5. the eighth raster-row is also stored in the cgrom, and should also be programmed. if the eighth raster-row is used for a cursor, this data should all be set to zero. 6. eprom data bits o7 to o5 are invalid. 0 should be written in all bits.
HD66705U 21 table 8 example of relationships between character code (ddram) and character pattern (cgram data) d7 d6 d5 d4 d3 d2 d1 d0 character code (ddram data) cgram data lsb msb a2 a1 a0 a4 a3 0 000 00 1 010 0 11 100 101 110 111 0 * * 0 0 0 0 10001 10001 10001 01010 00100 00100 00100 00000 0 0 *** o4 o3 o2 o1 o0 o5 o6 o7 cgram address 1 1 1 00000 ** 1 000 00 1 0 1 0 011 100 101 11 0 1 * * 0 0 0 0 10001 10001 10001 0 1 0 1 0 00100 00100 00 1 00 11 * character pattern (1) (don't care) (don't care) character pattern (4) notes: 1. the lower 2 bits of the character code correspond to the upper two bits of the cgram address (2 bits: 4 types). 2. cgram address bits 0 to 2 designate the character pattern raster-row position. the 8th raster- row is the cursor position and its display is formed by a logical or with the cursor. 3. the upper three bits of the cgram data are invalid; use the lower five bits. 4. when the upper four bits (bits 7 to 4) of the character code are 0, cgram is selected. bits 3 and 2 of the character code are invalid (*). therefore, for example, the character codes (00)h and (08)h correspond to the same cgram address. 5. a set bit in the cgram data corresponds to display selection, and 0 to non-selection. * indicates no effect.
HD66705U 22 table 9 correspondence between segment display segram addresses (aseg) and driver signals aseg address segment signals common msb lsb d7 d6 d5 d4 d3 d2 d1 d0 signal 1 0 0 0 * * * seg1, seg21, seg41 seg2, seg22, seg42 seg3, seg23, seg43 seg4, seg24, seg44 seg5, seg25, seg45 coms1 1 0 0 1 * * * seg6, seg26, seg46 seg7, seg27, seg47 seg8, seg28, seg48 seg9, seg29, seg49 seg10, seg30, seg50 coms1 1 0 1 0 * * * seg11, seg31, seg51 seg12, seg32, seg52 seg13, seg33, seg53 seg14, seg34, seg54 seg15, seg35, seg55 coms1 1 0 1 1 * * * seg16, seg36, seg56 seg17, seg37, seg57 seg18, seg38, seg58 seg19, seg39, seg59 seg20, seg40, seg60 coms1 1 1 0 0 * * * seg1, seg21, seg41 seg2, seg22, seg42 seg3, seg23, seg43 seg4, seg24, seg44 seg5, seg25, seg45 coms2 1 1 0 1 * * * seg6, seg26, seg46 seg7, seg27, seg47 seg8, seg28, seg48 seg9, seg29, seg49 seg10, seg30, seg50 coms2 1 1 1 0 * * * seg11, seg31, seg51 seg12, seg32, seg52 seg13, seg33, seg53 seg14, seg34, seg54 seg15, seg35, seg55 coms2 1 1 1 1 * * * seg16, seg36, seg56 seg17, seg37, seg57 seg18, seg38, seg58 seg19, seg39, seg59 seg20, seg40, seg60 coms2 notes: 1. when the sft pin is grounded, the seg1 pin output is connected to the far left of the lcd panel, and when the sft pin is high, the seg60 pin output is connected to the far left. 2. seg1 to seg20 data is identical to seg21 to seg40 and seg41 to seg60 data. 3. the lower five bits (d4 to d0) of segram data determine on or off display of each segment. a segment is selected (turned on) when the corresponding data is 1, and is deselected (turned off) when the corresponding data is 0. the upper three bits (d7 to d5) are invalid.
HD66705U 23 table 10 correspondence between annunciator display addresses (aan) and driver signals aan address annunciator segment signals common msb lsb d7 d6 d5 d4 d3 d2 d1 d0 signal 0 0 0 0 aseg1 blink aseg1 data aseg2 blink aseg2 data aseg3 blink aseg3 data aseg4 blink aseg4 data acom 0 0 0 1 aseg5 blink aseg5 data aseg6 blink aseg6 data aseg7 blink aseg7 data aseg8 blink aseg8 data acom 0 0 1 0 aseg9 blink aseg9 data aseg10 blink aseg10 data * * * * acom notes: 1. the annunciator is turned on when the corresponding even bit (data) is 1, and is turned off when 0. 2. the turned-on annunciator blinks when the corresponding odd bit (blink) is 1. blinking is provided by repeatedly turning on the annunciator for 32 frames and then turning it off for the next 32 frames.
HD66705U 24 instructions outline only the instruction register (ir) and the data register (dr) of the HD66705U can be controlled by the mpu. before starting internal operation of the HD66705U , control information is temporarily stored in these registers to allow interfacing with various peripheral control devices or mpus which operate at different speeds. the internal operation of the HD66705U is determined by signals sent from the mpu. these signals, which include register selection (rs), read/write (r/w), and the data bus (db0 to db7), make up the HD66705U instructions (table 17). there are four categories of instructions that: control display control power management set internal ram addresses perform data transfer with internal ram normally, instructions that perform data transfer with internal ram are used the most. however, auto- incrementation by 1 (or auto-decrementation by 1) of internal HD66705U ram addresses after each data write can lighten the program load of the mpu. while an instruction is being executed for internal operation, or during reset, no instruction other than the busy flag/address read instruction can be executed. because the busy flag is set to 1 while an instruction is being executed, check it to make sure it is 0 before sending another instruction from the mpu. if an instruction is sent without checking the busy flag, the time between the first instruction issue and next instruction issue must be longer than the instruction execution time itself. refer to table 16 for the list of each instruction execution cycles (clock pulses). the execution time depends on the operating clock frequency (oscillation frequency).
HD66705U 25 instruction description status read the status read instruction (figure 4) reads the busy flag (bf) indicating that the system is now internally operating on a previously received instruction. if bf is 1, the internal operation is in progress. the next instruction will not be accepted until bf is reset to 0. check the bf status before the next write operation. at the same time, the value of the address counter in binary aaaaaaa is read out. this address counter is used by both cgram, ddram, and segram addresses, and its value is determined by the previous instruction. clear display the clear display instruction (figure 5) writes space code (20)h (character pattern for character code (20)h must be a blank pattern) into all ddram addresses. it then sets ddram address 0 into the address counter. it also sets i/d to 1 (increment mode) in entry mode. 0 rs r/w db7 db0 1bfaaaaaaa figure 4 status read instruction 0000000001 rs r/w db7 db0 figure 5 clear display instruction
HD66705U 26 return home the return home instruction (figure 6) sets ddram address 0 into the address counter. the ddram contents do not change.the cursor or blinking goes to the top left of the display. start oscillator the start oscillator instruction (figure 7) re-starts the oscillator from a halt state in standby mode. after issuing this instruction, wait at least 10 ms for oscillation to become stable before issuing the next instruction. (refer to the standby mode section.) entry mode the entry mode instruction (figure 8) includes the i/d and osc bits. i/d: increments (i/d = 1) or decrements (i/d = 0) the ddram address by 1 when a character code is written into or read from ddram.the cursor or blinking moves to the right when incremented by 1 and to the left when decremented by 1. the same applies to writing and reading of cgram and segram. osc: divides the external clock frequency by four (osc = 1) using the resulting clock as an internal operating clock. the execution time for this instruction and subsequent ones is therefore quadrupled. the execution time of clearing this bit (osc = 0) is also quadrupled. (for application of this instruction, refer to the partial-display-off function section.) 0000000010 rs r/w db7 db0 figure 6 return home instruction 0000000011 rs r/w db7 db0 figure 7 start oscillator instruction
HD66705U 27 cursor control the cursor control (figure 9) includes the b/w, c, and b bits. b/w: when b/w is 1, the character at the cursor position is cyclically (every 32 frames) displayed with black-white inversion. c: the cursor is displayed on the 8th raster-row when c is 1. the cursor is displayed using 5 dots in the 8th raster-row for 5 8-dot character font. b: the character indicated by the cursor blinks when b is 1. the blinking is displayed as switching between all black dots and displayed characters every 32 frames. the cursor and blinking can be set to display simultaneously. when lc and b = 1, the blinking is displayed as switching between all white dots and displayed characters. figure 10 shows cursor control examples. 00000001i/d osc rs r/w db7 db0 figure 8 entry mode instruction 0000001b/wc b rs r/w db7 db0 figure 9 cursor control instruction
HD66705U 28 display on/off control the display on/off control instruction (figure 11) includes dc, ds, and lc bits. dc: the character display is on when dc is 1 and off when dc is 0. when off, the display data remains in ddram, and can be displayed instantly by setting dc to 1. ds: when ds = 1, segment display for icons and marks that is controlled by the multiplexing drive method is turned on and when ds = 0, it is turned off. when both dc and ds = 0, multiplexing drive is halted, setting the outputs from seg1 to seg60, com1 to com16 and coms1 and coms2 to v cc level to turn off the display. this can suppress current for lcd charging or discharging due to lcd driving operations. lc: when lc = 1, a cursor attribute is assigned to the line that contains the address counter (ac) value. cursor mode can be selected with the b/w, c, and b bits. refer to the line-cursor display section. alternating display (every 32 frames) alternating display i) white-black inverting display example ii) 8th raster-row cursor displa y ii) blink display example figure 10 cursor control examples 0000010dcds lc rs r/w db7 db0 figure 11 display on/off instruction
HD66705U 29 power control the cursor control instruction (figure 12) includes the amp, slp, and stb bits. amp: when amp = 1, each voltage-follower for v1 to v5 pins and the booster are turned on. when amp = 0, current consumption can be reduced while character or segment display controlled by the multiplexing drive method is not being used. slp: when slp = 1, the HD66705U enters sleep mode, where all the internal operations are halted except for annunciator display function and the r-c oscillator, thus reducing current consumption. refer to the sleep mode section. only the following instructions can be executed during sleep mode. a. annunciator address set (aan) b. annunciator data write c. annunciator display on or off (da = 1 or 0) d. voltage-follower on or off (amp = 1 or 0) e. standby mode set (stb = 1) f. sleep mode cancel (slp = 0) during sleep mode, other ram data and instructions cannot be updated but they are retained. stb: when stb = 1, the HD66705U enters standby mode, where the device completely stops, halting all the internal operations including the internal r-c oscillator and no external clock pulses are supplied. however, annunciator display alone is available when the alternating signal for annunciator-driving signals is supplied to the exm pin. when the annunciator display is not needed, make sure to turn off display (da = 0). refer to the standby mode section. only the following instructions can be executed during standby mode. a. annunciator address set (aan) b. annunciator data write c. annunciator display on or off (da = 1 or 0) d. voltage-follower on or off (amp = 1 or 0) e. start oscillator f. standby mode cancel (stb = 0) during standby mode, ram data and other instructions may be lost; they must be set again after standby mode is cancelled. 0000011ampslp stb rs r/w db7 db0 figure 12 power control instruction
HD66705U 30 display control the display control instruction (figure 13) includes the nl and dl bits. nl: designates the number of display lines. this value determines the lcd drive multiplexing duty ratio (table 11). the address assignment is the same for all display line modes. dl: doubles the height of characters on a specified line. the first line is doubled in height when dl = 1, two lines can be simultaneously doubled in a 2-line display. refer to the double-height display section. 0 rs r/w db7 db0 0 0 0 1 0nl0 0dl figure 13 display control instruction table 11 nl bits and display lines nl number of display lines lcd drive multiplexing duty ratio 0 1 1/10 1 2 1/18
HD66705U 31 contrast control the contrast control instruction (figure 14) includes the sn and ct bits. sn2: combined with the sn1 and sn0 bits described in the scroll control section to select the first line to be scrolled (display-start line). ct3?t0: controls the lcd drive voltage (potential difference between v cc and v5) to adjust contrast (figure 15 and table 12). refer to the contrast adjuster section. 0 0 0 1 0 sn2 ct3 ct2 ct1 ct0 rs r/w db7 db0 figure 14 contrast control instruction HD66705U v cc r + v1 r v2 r v3 r v4 r v5 v ee vr r + + + + figure 15 contrast adjuster
HD66705U 32 scroll control the scroll control instruction (figure 16) includes the sn and sl bits. sn1, sn0: combined with the sn2 bit described in the contrast control section to select the top line to be displayed (display-start line) through the data output from the com1 pin (table 13). after first five lines are displayed from the top line, the cycle is repeated and scrolling continues. table 12 ct bits and variable resistor value of contrast adjuster ct3 ct2 ct1 ct0 variable resistor value (vr) 0000 6.4 x r 0001 6.0 x r 0010 5.6 x r 0011 5.2 x r 0100 4.8 x r 0101 4.4 x r 0110 4.0 x r 0111 3.6 x r 1000 3.2 x r 1001 2.8 x r 1010 2.4 x r 1011 2.0 x r 1100 1.6 x r 1101 1.2 x r 1110 0.8 x r 1111 0.4 x r 0 0 0 1 1 sn1 sn0 sl2 sl1 sl0 rs r/w db7 db0 figure 16 scroll control instruction
HD66705U 33 sl2?l0: selects the top raster-row to be displayed (display-start raster-row) in the display-start line specified by sn2 to sn0. any raster-row from the first to eighth can be selected (table 14). this function is used to perform vertical smooth scroll together with sn2 to sn0. refer to the vertical smooth scroll section. table 13 sn bits and display-start lines sn2 sn1 sn0 display-start line 0 0 0 1st line 0 0 1 2nd line 0 1 0 3rd line 0 1 1 4th line 1 0/1 0/1 5th line table 14 sn bits and display-start raster-rows sl2 sn1 sl0 display-start raster-row 0 0 0 1st raster-row 0 0 1 2nd raster-row 0 1 0 3rd raster-row 0 1 1 4th raster-row 1 0 0 5th raster-row 1 0 1 6th raster-row 1 1 0 7th raster-row 1 1 1 8th raster-row
HD66705U 34 annunciator/segram address set the annunciator/segram address set instruction (figure 17) includes the da and a bits. da: turns annunciator display on or off. when da = 1, annunciator display is turned on and driven statically. when da = 0, annunciator display is turned off with aseg1 to aseg10 and acom pins held to v cc level. the internal operating clock supply is halted during standby mode; make sure to turn off display (da = 0) if the external alternating signal is not supplied. refer to the segment display and annunciator display section and the standby mode section. aaaa: used for setting the segram address in the address counter (ac) or for setting an annunciator address. the segram addresses range from 1000h to 1111h (8 addresses), while the annunciator addresses range from 0000h to 0010h (3 addresses). the annunciator address is directly set without using the address counter, and consequently must be updated for each access. the annunciator address can be set even during sleep and standby modes. once the segram address is set, data in the segram can be accessed consecutively since the address counter is automatically incremented or decremented by one according to the i/d bit setting after each access. the segram address cannot be set during sleep or standby mode. 0 rs r/w db7 db0 01 00daaaaa figure 17 annunciator/segram address set instruction
HD66705U 35 cgram address set the cgram address set instruction (figure 18) includes the a bits. aaaaa: used for setting the cgram address in the address counter (ac). the cgram addresses range from 00h to 1fh (32 addresses) (table 15). once the cgram address is set, data in the cgram can be accessed consecutively since the address counter is automatically incremented or decremented according to the i/d bit setting after each access. the cgram address cannot be set during sleep or standby mode. 0 rs r/w db7 db0 0101aaaaa figure 18 cgram address set instruction table 15 cgram addresses and character codes displayed character cgram address character codes 1st character 00h to 07h 00h 2nd character 08h to 0fh 01h 3rd character 10h to 17h 02h 4th character 18h to 1fh 03h
HD66705U 36 ddram address set the ddram address set instruction (figure 19) includes the a bits. aaaaaaa: used for setting the ddram address in the address counter (ac). the ddram addresses range from 00h to 4bh (60 addresses) (table 16). once the ddram address is set, data in the ddram can be accessed consecutively since the address counter is automatically incremented or decremented according to the i/d bit setting after each access. here, invalid addresses are automatically skipped. the ddram address cannot be set during sleep or standby mode. 0 rs r/w db7 db0 upper bits lower bits 0110000aa 00111aaaaa figure 19 ddram address set instruction table 16 ddram addresses and invalid addresses displayed line ddram address invalid addresses 1st line 00h to 0bh 0ch to 0fh 2nd line 10h to 1bh 1ch to 1fh 3rd line 20h to 2bh 2ch to 2fh 4th line 30h to 3bh 3ch to 3fh 5th line 40h to 4bh 4ch and subsequent addresses
HD66705U 37 write data to ram the write data to ram instruction (figure 20) writes 8-bit data to annunciator or ddram, or lower 5-bit data to segram or cgram that is selected by the previous specification of the address set instruction (annunciator/segram address set, cgram address set, or ddram address set). after a write, the address is automatically incremented or decremented by 1 according to the i/d bit setting in the entry mode instruction. the annunciator address is not automatically updated; it must be specifically updated to write data to a different address. during sleep and standby modes, ddram, cgram, or segram cannot be accessed. read data from ram the read data from ram instruction (figure 21), reads 8-bit data from ddram, or 5-bit binary data from cgram or segram that is selected by the previous specification of the address set instruction (segram address set, cgram address set, or ddram address set). the unused upper three bits of cgram or segram data are read as 000; annunciator data cannot be read. if no address is specified by the address set instruction just before this instruction, the first data read will be invalid. when executing serial read instructions, the next address is normally read from the next address. after a read, the address is automatically incremented or decremented by 1 according to the i/d bit setting in the entry mode instruction. table 17 lists the above instructions. 1 rs r/w db7 db0 0dddddddd figure 20 write data to ram instruction 1 rs r/w db7 db0 1dddddddd figure 21 read data from ram instruction
HD66705U 38 table 17 instruction list code execution instruction no. r/w rs db7 db6 db5 db4 db3 db2 db1 db0 description cycle * 1 status sr 1 0 bf ac ac ac ac ac ac ac reads busy flag (bf), which indicates internal operations are being performed, and reads address counter (ac). 0 clear display cl 0 0 0 0 0 0 0 0 0 1 clears entire display and sets ddram address 0 in address counter. 310 return home ch 0 0 0 0 0 0 0 0 1 0 sets ddram address 0 in address counter. 10 start oscillator os 0 0 0 0 0 0 0 0 1 1 starts oscillation during standby mode. entry mode set em 0 0 0 0 0 0 0 1 i/d osc sets address update direction after ram access (i/d), and system clock division (osc). 10 cursor control cr 0 0 0 0 0 0 1 b/w c b sets black-white inverting cursor (b/w), 8th raster- row cursor (c), and blink cursor (b). 10 display on/off control do 0 0 0 0 0 1 0 dc ds lc sets character display on/off (dc), segment display on/off (ds), and line-cursor on/off (lc). 10 power control pw 0 0 0 0 0 1 1 amp slp stb turns on voltage-follower and booster (amp), and sets sleep mode (slp) and standby mode (stb). 10 display control dc 0 0 0 0 1 0 nl 0 0 dl sets the number of display lines (nl) and the line to be doubled in height. 10 contrast control cn 0 0 0 1 0 sn2 ct3 ct2 ct1 ct0 sets the display-start line (sn2) and contrast- adjusting value (ct). 10 scroll control sc 0 0 0 1 1 sn1 sn0 sl2 sl1 sl0 sets the display-start line (sn) and display-start raster-row (sl). 10 annunciator /segram address set as 0 0 1 0 0 da aan/ a seg3 aan/ a seg2 aan/ a seg1 aan/ a seg0 turns on annunciator display and sets annunciator/segram address. 10 cgram address set ca00101a cg4 a cg3 a cg2 a cg1 a cg0 sets the initial cgram address to the address counter. 10 ddram address set (upper bits) da00110000a dd6 a dd5 sets the initial higher ddram address to the address counter. 10 ddram address set (lower bits) da00111a dd4 a dd3 a dd2 a dd1 a dd0 sets the initial lower ddram address to the address counter. 10
HD66705U 39 table 17 instruction list (cont) code execution instruction no. r/w rs db7 db6 db5 db4 db3 db2 db1 db0 description cycle * 1 write data to ram wd 0 1 write data writes data to ddram, cgram, segram, or annunciator. 10 read data from ram rd 1 1 r ead data reads data from ddram, cgram, or segram. 10 bf = 1: internally operating ac: address counter i/d = 1: increment i/d = 0: decrement osc = 1: system clock divided by four b/w = 1: black-white inverting cursor on c = 1: 8th raster-row cursor on b = 1: blink cursor on d = 1: display on dc = 1: character display on ds = 1: segment display on lc = 1: line containing ac given cursor attribute amp = 1: voltage-follower and booster on slp = 1: sleep mode stb = 1: standby mode nl : number of display lines [0: 1line (1/10 duty ratio), 1: 2 lines (1/18 duty ratio)] d l=1 :double-height line ct3?t0: contrast adjustment s n 2 sn0: display-start line (000: 1st line, 001: 2nd line, 010: 3rd line, 011: 4th line, 100: 5th line) sl2 ?sl0: display-start raster-row (000: 1st raster-row... 111: 8th raster-row) da = 1: annunciator display on aan/a seg = 0000?010: annunciator address aan/a seg = 1000?111: segram address acg4?cg0: cgram address (00000?1111) add6?dd0: ddram address (0000000?001011) note: 1. represented by the number of operating clock pulses; the execution time depends on the supplied clock frequency or the internal oscillation frequency.
HD66705U 40 reset function initializing by internal reset circuit the HD66705U is internally initialized by reset input. during reset, the system executes the instructions as described below. here, the busy flag (bf) therefore indicates a busy state (bf = 1), accepting no instruction or ram data access from the mpu. here, reset input must be held at least 10 ms. after releasing power-on reset, clear display instruction is operated, so wait for 1,000 clock-cycles or more. make sure to reset the HD66705U immediately after power-on rese. 1. instruction set initialization a. clear display: writes 20h to ddram and wait for 1,000 clock-cycles or more after releasing reset b. return home sets the address counter (ac) to 00h to select the ddram c. start oscillator d. entry mode i/d = 1: increment by 1 osc = 0: clock frequency not divided e. cursor control b/w = 0: white-black inverting cursor off c = 0: 8th raster-row cursor off b = 0: blink cursor off f. display on/off control dc = 0: character display off ds = 0: segment display off lc = 0: line-cursor off g. power control amp = 0: lcd power supply off slp = 0: sleep mode off stb = 0: standby mode off h. display control dl = 0: double-height display off i. contrast adjust ct = 0000: weak contrast j. scroll control sn2?n0 = 000: first line displayed at the top sl2?l0 = 000: first raster-row displayed at the top of the first line
HD66705U 41 k. annunciator control da = 0: annunciator display off 2. ram data initialization a. ddram all addresses are initialized to 20h by the clear display instruction b. cgram/segram not automatically initialized by reset input; must be initialized by software while display is off (dc and ds = 0) c. annunciator data not automatically initialized by reset input; must be initialized by software while display is off (da= 0) 3. output pin initialization a. lcd driver output pins (seg/com, aseg/acom): outputs v cc level b. booster output pins (v5out2 and v5out3): outputs gnd level c. oscillator output pin (osc2): outputs oscillation signal
HD66705U 42 transferring serial data clock-synchronized serial interface setting the im1 and im0 pins (interface mode pins) to the gnd and high levels, respectively, allows standard clock-synchronized serial data transfer, using the chip select (cs*), sda, and scl lines. here, the HD66705U exclusively receives data. the HD66705U initiates serial data transfer by transferring the start byte at the falling edge of the cs* input. it ends serial data transfer at the rising edge of the cs* input. the HD66705U is selected when the 6-bit chip address in the start byte transferred from the transmitting device matches the 6-bit (device) identification code assigned to the HD66705U . the HD66705U , when selected, receives the subsequent data strings. any identification code can be assigned by the db5/id5 to db0/id0 pins. two different chip addresses must be assigned to a single HD66705U because the seventh bit of the start byte is used as a register select bit (rs): when rs = 0, an instruction can be issued and when rs = 1, data can be written to a ram. the eighth bit of the start byte must be 0. after receiving the start byte, the HD66705U receives the subsequent data as an HD66705U instruction or as ram data. data is transferred with the msb first. to transfer data consecutively, adjust the data transfer rate so that the HD66705U can complete the current instruction before the eighth bit of the next instruction is transferred. see table 17, instruction list. if the next instruction is received during execution of the previous instruction, the next instruction will be ignored. note that the display-clear instruction alone requires longer execution time than the others. figure 23 shows the clock-synchronised serial interface timing sequence.
HD66705U 43 (a) basic data transfer (receive) timing (b) consecutive data transfer timing start byte instruction 1234 56789101112131415161718192021222324 d7 d6 d5 d4 0 2nd instruction device id code 1st instruction scl (input) sda (input) cs* (input) id5 id4 id3 id2 id1 id0 rs d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 transfer start transfer end msb rs 1st byte instruction 1 execution time scl (input) sda (input) 123 456 78 910111213141516 171819 instruction 1 instruction 2 20 21 22 23 24 25 26 27 28 29 30 31 32 instruction 2 execution time instruction 3 start end note: adjust the transfer rate so that the hd66717 can complete instruction 1 before the 8th bit of instruction 2 is transferred. cs* (input) figure 23 clock-synchronized serial interface timing sequence
HD66705U 44 transferring parallel data interface with an 8-bit mpu eight-bit data can be transferred in parallel by setting the im1 and im0 pins to the v cc and gnd levels, respectively (figure 24). the HD66705U can interface directly with an 8-bit bus synchronized with the e clock, or with an 8-bit mcu through an i/o port (figure 25). when the number of i/o lines or chip packaging size is limited, a 4-bit bus interface or even serial data transfer should be used. r/w e internal signal db7 internal operation data busy busy not busy data instruction write busy flag check busy flag check busy flag check instruction write rs figure 24 8-bit parallel data transfer timing sequence e rs r/w db0 - db7 c0 c1 c2 a0 - a7 h8/325 HD66705U 8 i/o port interface figure 25 8-bit mpu interface
HD66705U 45 interface with a 4-bit mpu four-bit data can be transferred in parallel by setting both the im1 and im0 pins to the v cc level (figure 26). four-bit data representing higher or lower bits of 8-bit instructions or 8-bit ram data can be transferred in that order. the HD66705U can forcibly reset the counter that counts the number of higher and lower 4-bit data transfers in a 4-bit bus interface. this function, called transfer-syncronization, can be performed by writing a special instruction containing 0000 four consecutive times (figure 27). for example, when a data transfer sequence becomes disordered due to noise or some undesired factor, this function resets the counter and thus enables resuming data transfer from the higher 4 bits. using this function at specified intervals prevents display- system crash. ir7 busy not busy ir3 ac3 ac3 d7 d3 instruction write busy flag check internal operation busy flag check instruction write r/w e internal signal db7 rs figure 26 4-bit parallel data transfer timing sequence 0000 0000 0000 0000 rs r/w e db7 db0 higher lower ( 4-bit data transfer s y nchronized ) (1) (2) (3) (4) figure 27 4-bit data transfer synchronization
HD66705U 46 oscillator circuit the HD66705U can either be supplied with operating clock pulses externally (external clock mode) or oscillate using an internal r-c oscillator and an external oscillator-resistor (internal oscillation mode), as shown in figure 28. an appropriate oscillator-resistor must be used to obtain the optimum clock frequency according to the number of display lines (table 18). instruction execution times change in proportion to the operating clock frequency or r-c oscillation frequency; mpu data transfer rate must be appropriately adjusted (see table 17, instruction list). figure 29 shows a sample lcd drive output waveform, where 2- lines are displayed with 1/18 multiplexing duty ratio. osc1 osc1 osc2 clock rf the oscillator frequency can be adjusted by oscillator resistance (rf). if rf is increased or power supply voltage is decreased, the oscillator frequency decreases. HD66705U 1) when an external clock is used 2) when an internal oscillator is used HD66705U figure 28 oscillator circuit table 19 oscillation frequency and lcd frame frequency item 1-line display nl = 0 2-line display nl = 1 multiplexing duty ratio 1/10 1/18 oscillator resistance (r f )v cc = 3v 620 k w 300 k w cr oscillator frequency 45 khz 95 khz frame frequency 75 hz 88 hz
HD66705U 47 1 234 17 18 123 17 18 v cc v1 v4 v5 com1 1-line selection period v1 v4 v5 com2 1 frame v cc v1 v4 v5 coms2 v cc v1 v4 v5 coms1 v cc 1 frame figure 29 lcd drive output waveform example (2-line display with 1/18 multiplexing duty ratio)
HD66705U 48 power supply for liquid crystal display drive when external power supply and internal operational amplifiers are used to supply lcd drive voltage directly from the external power supply without using the internal booster, circuits should be connected as shown in figure 30. here, contrast can be adjusted through the ct bits of the contrast-control instruction. the HD66705U incorporates a voltage-follower operational amplifier for each of v1 to v5 to reduce current flowing through the internal bleeder-resistors, which generate different levels of liquid-crystal drive voltages. thus, potential differences between v cc and v1 and between v ee and v5 must be 0.4v or greater. note that the opoff pin must be grounded when using the operational amplifiers. v cc v2 v3 v cc r v1 v2 v3 v4 v5 r r r r v ee vr + + + + seg1?eg60 com1?om16 coms1?oms2 gnd agnd aseg1?seg10 acom + v ee HD66705U opoff = gnd 1- or 2-line display with 1/4 bias note: 1. potential differences between v cc and v1 and between v5 and v ee must be 0.4v or greater, particularly for low-duty drive such as 1-line display. 2. when using the internal operational amplifiers, an capacitor must be inserted between each output of v1out and v4out, and v cc to stabilize the operational amplifier output. if the internal operational amplifiers cannot fully drive the lcd panel used, an appropriate capacitor must be inserted between another outputs (v2out, v3out, v5out) and v cc. lcd multiplexing driver lcd static driver v2 - v3: short-circuit v4out v1out 0.1uf to 0.5uf figure 30 external power supply circuit example for lcd drive voltage generation
HD66705U 49 when an internal booster and internal operational amplifiers are used to supply lcd drive voltage using the internal booster, circuits should be connected as shown in figure 31. here, contrast can be adjusted through the ct bits of the contrast-control instruction. temperature can be compensated either through the ct bits or by controlling the reference voltage for the booster (vci pin) using a thermistor. note that vci is both a reference voltage and power supply for the booster; the reference voltage must therefore be adjusted using an emitter-follower or a similar element so that sufficient current can be supplied. in this case, vci must be equal to or smaller than the v cc level. the HD66705U incorporates a voltage-follower operational amplifier for each of v1 to v5 to reduce current flowing through the internal bleeder-resistors, which generate different levels of liquid-crystal drive voltages. thus, potential differences between v cc and v1 and between v ee and v5 must be 0.4v or greater. note that the opoff pin must be grounded when using the operational amplifiers.
HD66705U 50 b) triple boosting c1 c2 vci v5out2 v5out3 + gnd + v cc v2 v3 v cc r v1 v2 v3 v4 v5 r r r r vr + + + + + v ee booster gnd + opof = gnd 0.47 m f to 1 m f 0.47 m f to 1 m f HD66705U note: 1. the reference voltage input (vci) must be adjusted so that the output voltage after boosting will not exceed the absolute maximum rating of the liquid-crystal power supply voltage (11v). particularly, vci must be 4 v or less for triple boosting. 2. vci is both a reference voltage and power supply for the booster; connect it to v cc directly or combine it with a transistor so that sufficient current can be obtained. 3. vci must be smaller than v cc . 4. to operate the voltage-follower correctly, potential differences between v cc and v1 and between v5 and v ee must be 0.4v or greater, particularly for low-duty drive such as 1-line display. 5. polarized capacitors must be connected correclty. 6. circuits for temperature compensation should be designed based on the sample circuit shown in figure 32. 7. when using the internal operational amplifiers, an capacitor must be inserted between each output of v1out and v4out, and v cc to stabilize the operational amplifier output. if the internal operational amplifiers cannot fully drive the lcd panel used, an appropriate capacitor must be inserted between another outputs (v2out, v3out, v5out) and v cc. a) double boosting c1 c2 vci v5out2 v5out3 + gnd + v cc v2 v3 v cc r r r r r vr v ee opoff = gnd c1 c2 vci v5out2 v5out3 + gnd + v2 v3 r r r r r vr booster 0.47 m f to 1 m f 0.47 m f to 1 m f HD66705U + + + + + v1 v2 v3 v4 v5 v1out v4out v4out v1out 0.1 m f to 0.5 m f 0.1 m f to 0.5 m f figure 31 internal power supply circuit example for lcd drive voltage generation
HD66705U 51 v cc thermistor gnd tr v cc vci HD66705U figure 32 temperature compensation circuit example
HD66705U 52 the HD66705U ? internal operational amplifiers have a reduced drive current to save current consumption; when the internal operational amplifiers cannot fully drive the lcd panel used, an appropriate capacitors must be inserted between each output of v1out to v5out and v cc to stabilize the operational amplifier output (figure 33). especially, the capacitors for v1out and v4out must be inserted. c1 c2 vci v5out2 v5out3 + gnd + v cc v2 v3 v cc r r r r vr + + + + + v ee booster + 0.47 m f to 1 m f 0.47 m f to 1 m f 0.47 m f to 1 m f opoff = gnd v5out3 v2 r gnd + HD66705U v1out + v2out v3out v4out v5out + + + + seg1?eg60 com1?om16 coms1?oms2 lcd multiplexing driver v cc v1 v2 v3 v4 v5 0.1 f to 0.5 f* note : the capacitors for v1out and v4out must be inserted . figure 33 operational amplifier output stabilization circuit example
HD66705U 53 when an internal booster and external bleeder-resistors are used when the internal operational amplifiers cannot fully drive the lcd panel used, v1 to v5 voltages can be supplied through external bleeder-resistors (figure 34). here, the opoff pin must be set to the v cc level to turn off the internal operational amplifiers. since the internal contrast adjuster is disabled in this case, contrast must be adjusted externally. double- and triple-boosters can be used as they are. c1 c2 vci v5out2 v5out3 + gnd + v cc v1out v2out v3out v4out v5out v cc note: 1. resistance of each external bleeder resistor should be 5 k w to 20 k w . 2. the bias current value for driving liquid-crystals can be varied by adjusting the resistance (r) between the v2out and v3out pins. 3. the internal contrast-adjuster is disabled; contrast must be adjusted either by controlling the external variable resistor between v ee and v5out or vci for the booster. 4. vci is both a reference voltage and power supply for the booster; connect it to v cc directly or combine it with a transistor so that sufficient current can be obtained. 5. vci must be smaller than v cc . + + + + + v ee booster gnd + 0.47 m f to 1 m f 0.47 m f to 1 m f 0.47 m f to 1 m f HD66705U opoff = v cc r r r r vr r v cc v1 v2 v3 v4 v5 c1 c2 vci v5out2 v5out3 + gnd + v cc v1out v2out v3out v4out v5out v cc + + + + + v ee booster gnd + 0.47 m f to 1 m f 0.47 m f to 1 m f 0.47 m f to 1 m f HD66705U opoff = v cc r r r r vr v cc v1 v2 v3 v4 v5 a) 1/5 bias driving with the external resistors b) 1/4 bias driving with the external resistors figure 34 external bleeder-resistor example for lcd drive voltage generation power supply circuit
HD66705U 54 contrast adjuster multiplexing drive system contrast for an lcd controlled by the multiplexing drive method can be adjusted by varying the liquid- crystal drive voltage (potential difference between v cc and v5) through the ct bits of the contrast control instruction (electron volume function). see figure 35 and table 20. the value of a variable resistor (vr) can be adjusted within the range from 0.4r through 6.4r, where r is a reference resistance obtained by dividing the total resistance between v cc and v5. the HD66705U incorporates a voltage-follower operational amplifier for each of v1 to v5 to reduce current flowing through the internal bleeder-resistors, which generate different levels of liquid-crystal drive voltages. thus, potential differences between v cc and v1 and between v ee and v5 must be 0.4v or greater. note that the opoff pin must be grounded when using the operational amplifiers. 1/4 bias (v2 and v3 pins short-circuited) ? lcd drive voltage vlcd: 4r (v cc ?v ee )/(4r + vr) (vr = a value within the range from 0.4r to 6.4r) ? vlcd adjustable range: 0.385 (v cc ?v ee ) vlcd 0.909 (v cc ?v ee ) ? potential difference between v cc and v1: r (v cc ?v ee )/(4r + vr) 3 0.4 (v) ? potential difference between v5 and v ee : vr (v cc ?v ee )/(4r + vr) 3 0.4 (v) 1/5 bias (v2 and v3 pins open) ? lcd drive voltage vlcd: 5r (v cc ?v ee )/(5r + vr) (vr = a value within the range from 0.4r to 6.4r) ? vlcd adjustable range : 0.439 (v cc ?v ee ) vlcd 0.926 (v cc ?v ee ) ? potential difference between v cc and v1 : r (v cc ?v ee )/(5r + vr) 3 0.4(v) ? potential difference between v5 and v ee : vr (v cc ?v ee )/(5r + vr) 3 0.4(v) static drive system contrast for a statically-driven lcd, that is, annunciator display, can be adjusted through the agnd pin. the annunciators are driven statically by the potential difference between v cc and agnd. the agnd pin level must be equal to or greater than the gnd level.
HD66705U 55 v cc v cc v2-v3 : v2-v3 : short-circuited when 1/4 bias driving. open when 1/5 bias driving. v2 v3 r v1 ct v2 v3 v4 v5 r r r r vr + + + + + v ee HD66705U figure 35 contrast adjuster table 20 contrast-adjust bits (ct) and variable resistor values ct register ct3 ct2 ct1 ct0 variable resistor value (vr) 0 0 0 0 6.4 r 0 0 0 1 6.0 r 0 0 1 0 5.6 r 0 0 1 1 5.2 r 0 1 0 0 4.8 r 0 1 0 1 4.4 r 0 1 1 0 4.0 r 0 1 1 1 3.6 r 1 0 0 0 3.2 r 1 0 0 1 2.8 r 1 0 1 0 2.4 r 1 0 1 1 2.0 r 1 1 0 0 1.6 r 1 1 0 1 1.2 r 1 1 1 0 0.8 r 1 1 1 1 0.4 r
HD66705U 56 lcd module interface segment data output pins seg1 to seg60 can be connected either from left to right or right to left of an lcd panel according to the sft pin level. when the sft pin is grounded, seg1 is connected to the far left of the panel, and when it is at the v cc level, seg60 is connected to the far left. either connection mode can be selected according to the lcd module layout and routing on a printed-circuit board. figures 36 shows two examples.
HD66705U 57 b) 12-character x 2-line display (seg line below the panel : sft = v cc ) a) 12-character x 2-line display (seg line above the panel : sft = gnd) gnd HD66705U seg60 seg59? seg1 coms1 coms2 acom aseg1? aseg10 on mode 2ndf clock date time key com1 ? com8 com9 ? com16 sft com1 ? com8 com9 ? com16 seg60 seg59? seg1 coms1 coms2 acom v cc sft HD66705U aseg1? aseg10 on mode mode 2ndf clock date time key figure 36 lcd module interface examples
HD66705U 58 segment display and annunciator display the HD66705U provides both segment display, which is driven by the multiplexing method, and annunciator display, which is driven statically. annunciator display is driven at a logic operating voltage (v cc agnd) and is thus also available while the lcd drive power supply is turned off. accordingly, annunciator display is suitable for displaying marks during system standby, when it is desirable to reduce current consumption. it is available in sleep mode, where internal multiplexing operations for character or segment display are halted. if an alternating signal is supplied to the exm pin, it is also available in standby mode, where the internal r-c oscillator is halted. here, agnd must be equal to or above the gnd level. note that annunciator display cannot share character display drivers seg and com but require special drivers aseg and acom that require long routing. tables 21 to 23 illustrates segment display and annunciator display. table 21 comparison between segment display and annunciator display item segment display annunciator display number of driven elements 20 each by coms1 and coms2 10 blinking impossible possible segment drivers seg1?eg60 (shared with character display) aseg1?seg10 (independent of character display) common drivers coms1, coms2 acom lcd power supply v cc ?v5 (lcd power supply necessary) v cc ?agnd (lcd power supply unnecessary) normal mode display display possible together with character display by multiplexing drive display possible by static drive sleep mode display impossible (seg and com output v cc ) possible by static drive standby mode display (without oscillation) impossible (seg and com output v cc ) possible by supplying alternating signal to the exm pin
HD66705U 59 table 22 correspondence between segment display segram addresses (aseg) and driver signals aseg address common segment signals msb lsb signal bit 4 bit 3 bit 2 bit 1 bit 0 1 0 0 0 coms1 seg1/21/41 seg2/22/42 seg3/23/43 seg4/24/44 seg5/25/45 1 0 0 1 coms1 seg6/26/46 seg7/27/47 seg8/28/48 seg9/29/49 seg10/30/50 1 0 1 0 coms1 seg11/31/51 seg12/32/52 seg13/33/53 seg14/34/54 seg15/35/55 1 0 1 1 coms1 seg16/36/56 seg17/37/57 seg18/38/58 seg19/39/59 seg20/40/60 1 1 0 0 coms2 seg1/21/41 seg2/22/42 seg3/23/43 seg4/24/44 seg5/25/45 1 1 0 1 coms2 seg6/26/46 seg7/27/47 seg8/28/48 seg9/29/49 seg10/30/50 1 1 1 0 coms2 seg11/31/51 seg12/32/52 seg13/33/53 seg14/34/54 seg15/35/55 1 1 1 1 coms2 seg16/36/56 seg17/37/57 seg18/38/58 seg19/39/59 seg20/40/60 table 23 correspondence between annunciator display addresses (aan) and driver signals aan address common segment signals msb lsb signal bits 7, 6 bits 5, 4 bits 3, 2 bits 1, 0 0 0 0 0 acom aseg1 aseg2 aseg3 aseg4 0 0 0 1 acom aseg5 aseg6 aseg7 aseg8 0 0 1 0 acom aseg9 aseg10 note: the annunciator is turned on when the corresponding even bit (bit 6, 4, 2, or 0) is 1, and the turned- on annunciator blinks when the corresponding odd bit (bit 7, 5, 3, or 1) is 1.
HD66705U 60 annunciator drive figure 37 shows annunciator drive output waveforms in two modes. i) normal mode and sleep mode ii) standby mode (without oscillation) v cc level v cc level v cc level agnd level agnd level agnd level agnd level agnd level v cc level v cc level v cc level v cc level display off display on 1 frame acom aseg1 aseg2 exm (input) v cc level v cc level v cc level agnd level agnd level agnd level v cc level v cc level v cc level acom aseg1 aseg2 display off display on 1 frame note: if annunciator display is unnecessary during standby mode, make sure to fix the exm pin to the v cc or gnd level and set the annunciator display on bit (da) to 0. this will prevent dark display and liquid-cell deterioration due to dc bias application on liquid crystal cells. figure 37 annunciator drive output waveforms
HD66705U 61 vertical smooth scroll the HD66705U can scroll in the vertical direction in units of raster-rows. this function is achieved by writing character codes into the ddram area that is not being used for display. in other words, since the ddram corresponds to a 5-line 12-character display, one of the lines can be used to achieve continuous smooth vertical scroll even in a 4-line display. here, after the fifth line is displayed, the first line is displayed again. specifically, this function is controlled by incrementing or decrementing the value in the scroll-start line bits (sl2 to sl0) and scroll-start raster-row bits (sn2 to sn0) by 1. for example, to smoothly scroll up, first set sn2 to sn0 to 000, and increment sl2 to sl0 by 1 from 000 to 111 to scroll seven raster-rows. then increment sn2 to sn0 to 001, and again increment sl2 to sl0 by 1 from 000 to 111. to start displaying and scrolling from the first raster-row of the second line, update the first line of ddram data as desired during its non-display period. figure 38 shows an example of vertical smooth scrolling and figure 39 shows an example of setting instructions for vertically scrolling upward in a 2-line display (nl = 1).
HD66705U 62 i) normal display ii) 1 raster-line scroll iii) 2 raster-lines scroll iv) 3 raster-lines scroll v) 4 raster-lines scroll figure 38 example of vertical smooth scrolling
HD66705U 63 db7 db6 db5 db4 db3 db2 db1 db0 r/w rs 0000 1 0 ct sn2="0" 0001 0 0 sn1/0 = "00", sl2 to 0 = "000" (starts from the first raster-line in the first line) 0 0 1 mpu wait initial set ddram data for 5 lines 1 raster-line upward scroll (starts from the 2nd raster-line in the first line) 0 0001 0 1 0 0 1 0 mpu wait 2 raster-lines upward scroll (starts from the 3nd raster-line in the first line) 0001 10 0 0 1 0 mpu wait 3 raster-lines upward scroll (starts from the 4th raster-line in the first line) 0001 1 1 0 0 1 0 mpu wait 4 raster-lines upward scroll (starts from the 5th raster-line in the first line) 0001 0 0 1 0 1 0 mpu wait 7 raster-lines upward scroll (starts from the 8th raster-line in the first line) 0 001 1 1 1 0 1 0 mpu wait 8 raster-lines upward scroll (starts from the first raster-line in the 2nd line) 0 001 00 0 1 1 0 update ddram data for first line (address : "00" to "0b" h) displaying 2nd and 3rd line mpu wait 9 raster-lines upward scroll (starts from the 2nd raster-line in the 2nd line) 0001 0 1 0 1 1 0 mpu wait 16 raster-lines upward scroll (starts from the first raster-line in the 3rd line) 0001 0 0 0 0 1 1 update ddram data for 2nd line (address : "10" to "1b" h) displaying 3rd and 4th line mpu wait 17 raster-lines upward scroll (starts from the 2nd raster-line in the 3rd line) 0001 0 1 0 0 1 1 figure 39 example of setting instructions for vertical smooth scroll (2-line display (nl = 1))
HD66705U 64 line-cursor display the HD66705U can assign a cursor attribute to an entire line corresponding to the address counter value by setting the lc bit to 1 (table 24). one of three line-cursor modes can be selected: a black-white inverting blink cursor (b/w = 1), an underline cursor (c = 1), and a blink cursor (b = 1). the blink cycle for a black- white inverting blink cursor and for a blink cursor is 32 frames. these line-cursors are suitable for highlighting an index and/or marker, and for indicating an item in a menu with a cursor or an underline. figures 40 to 42 show three line-cursor examples. table 24 address counter value and line-cursor address counter value (ac) selected line for line-cursor 00h to 0bh entire 1st line (12 digits) 10h to 1bh entire 2nd line (12 digits) 20h to 2bh entire 3rd line (12 digits) 30h to 3bh entire 4th line (12 digits) 40h to 4bh entire 5th line (12 digits) alternating display for every 32 frames figure 40 example of black-white inverting blink cursor (lc = 1; b/w = 1)
HD66705U 65 figure 41 example of underline cursor (lc = 1; c = 1) alternating display for evry 32 frames figure 42 example of blink cursor (lc = 1; b = 1)
HD66705U 66 double-height display the HD66705U can double the height of any desired line from the first lines a line can be selected by the dl bit as listed in table 25. all the standard font characters stored in the cgrom and cgram can be doubled in height, providing an easy-to-see display. note that there should be no space between lines for double-height display (figure 43). table 25 double-height display specifications dl 2-line display (nl = 1) 0 1st & 2nd lines: normal display 1 1st line: double-height display i) example of normal display in 2 lines mode (when dl="0") ii) example of double height display (when dl="1") fi r st l i ne di sp l ay d oubl e hei ght di sp l ay 2nd l i ne di sp l ay figure 43 double-height display examples
HD66705U 67 sleep mode setting the sleep mode bit (slp) to 1 puts the HD66705U in sleep mode, where the device halts all the internal display operations except for annunciator display operations, thus reducing current consumption. specifically, character and segment displays, which are controlled by the multiplexing drive method, are completely halted. here, all the seg (seg1 to seg60) and com (com1 to com16, coms?/2) pins output the v cc level, resulting in no display. if the amp bit is set to 0 in sleep mode, the lcd drive power supply can be turned off, reducing the total current consumption of the lcd module. annunciators can be normally displayed in sleep mode. since they are driven at logic operating power supply voltage (v cc ?agnd), they are available even if the lcd power supply is turned off (amp = 0). this function allows time and alarm marker indication during system standby with reduced current consumption. during sleep mode, no instructions can be accepted for character/segment display and neither ddram, cgram, nor segram can be accessed. table 27 compares the functions of sleep mode and standby mode. table 27 comparison of sleep mode and standby mode function item sleep mode (slp = 1) standby mode (stb = 1) character display turned off turned off segment display turned off turned off annunciator display can be turned on can be turned on when an alternating signal is supplied to the exm pin r-c oscillation normally operates halted
HD66705U 68 standby mode setting the standby mode bit (stb) to 1 puts the HD66705U in standby mode, where the device stops completely, halting all internal operations including the r-c oscillator, thus further reducing current consumption compared to that in sleep mode. specifically, character and segment displays, which are controlled by the multiplexing drive method, are completely halted. here, all the seg (seg1 to seg60) and com (com1 to com16, coms1/2) pins output the v cc level, resulting in no display. if the amp bit is set to 0 in standby mode, the lcd drive power supply can be turned off. annunciators can be displayed simply by supplying an approximately 40-hz alternating signal for the lcd drive signals to the exm pin externally. if annunciator display is unnecessary during standby mode, the exm pin must be fixed to the v cc or gnd level and the annunciator display-on bit (da) set to 0. during standby mode, no instructions can be accepted other than those for annunciator display and the start-oscillator instruction. to cancel standby mode, issue the start-oscillator instruction to stabilize r-c oscillation before setting the stb bit to 0. figure 45 shows the procedure for setting and cancelling standby mode. turn off the lcd power supply: amp = 0 only for annunciator display; set the da bit to 0 when annunciator display is not necessary. set standby mode: stb = 1 supply an external alternating signal to the exm pin issue the start-oscillator instruction wait at least 10 ms cancel standby mode: stb = 0 turn on the lcd drive power supply: amp = 1 standby mode (only annunciator display is available) figure 45 procedure for setting and cancelling standby mode
HD66705U 69 absolute maximum ratings* item symbol unit value notes power supply voltage (1) v cc v ?.3 to +7.0 1 power supply voltage (2) v cc ? ee v ?.3 to +11.0 1, 2 input voltage vt v ?.3 to v cc + 0.3 1 operating temperature t opr c ?0 to +85 storage temperature t stg c ?5 to +110 4 note: * if the lsi is used above these absolute maximum ratings, it may become permanently damaged. using the lsi within the following electrical characteristic limits is strongly recommended for normal operation. if these electrical characteristic conditions are also exceeded, the lsi will malfunction and cause poor reliability.
HD66705U 70 dc characteristics (v cc = 2.4v to 5.5v, t a = ?0 to +85 c* 3 ) item symbol min typ max unit test condition notes* input high voltage vih 0.7v cc ? cc v 6, 7 input low voltage vil ?.3 0.15v cc vv cc = 2.4 to 3.0v 6, 7 ?.3 0.6 v v cc = 3.0 to 5.5v output high voltage (1) (db0?b7 pins) voh1 0.75v cc v i oh = ?.1 ma output low voltage (1) (db0?b7 pins) vol1 0.2v cc vi ol = 0.1 ma driver on resistance (com pins) r com 2 20 k w id = 0.05 ma (com) vlcd = 4v 8 driver on resistance (seg pins) r seg 2 30 k w id = 0.05 ma (seg) vlcd = 4v 8 i/o leakage current i li ? 1 m av in = 0 to v cc 9 pull-up mos current (reset* pin) ?p 10 50 120 m av cc = 3v vin = 0v current consumption during normal operation (v cc ?nd) i op ?550 m ar f oscillation, external clock, v cc = 3v, f osc = 95 khz, 1/18 duty 10, 11 current consumption during sleep mode (v cc ?nd) i sl ?2 m ar f oscillation, external clock, v cc = 3v, f osc = 95 khz 10, 11 current consumption during standby mode (v cc ?nd) i st 0.1 5 m a no r f oscillation, v cc = 3v, ta = 25 c 10, 11 lcd power supply current (v cc ? ee ) i ee ?550 m av cc ? ee = 5.5v, f osc = 95 khz vref?refm-vrefp: short-circuited lcd voltage with 1/4 bias (v cc ? ee ) v lcd1 3.0 9.0 v v2?3: short-circuited 12 lcd voltage with 1/5 bias (v cc ? ee ) v lcd2 3.0 9.0 v v2?3: open 12 note: * refer to the electrical characteristics notes section following these tables.
HD66705U 71 booster characteristics item symbol min typ max unit test condition notes* output voltage (v5out2 pin) vup2 8.0 8.8 v v cc = vci = 4.5v, i 0 = 0.1 ma, c = 1 m f, f osc = 95 khz, t a = 25 c 15 output voltage (v5out3 pin) vup3 7.0 7.9 v v cc = vci = 2.7v, i 0 = 0.1 ma, c = 1 m f, f osc = 95 khz, t a = 25 c 15 input voltage vci 1.0 5.0 v vci v cc 15 note: * refer to the electrical characteristics notes section following these tables.
HD66705U 72 ac characteristics (v cc = 2.4v to 5.5v, t a = ?0 to +85 c* 3 ) clock characteristics (v cc = 2.4v to 5.5v) item symbol min typ max unit test condition notes* external external clock frequency f cp 20 95 350 khz 13 clock external clock duty ratio duty 45 50 55 % operation external clock rise time t rcp 0.2 m s external clock fall time t fcp 0.2 m s r f oscillation clock oscillation frequency f osc 70 95 120 khz r f = 300 k w , v cc = 3v 14 note: * refer to the electrical characteristics notes section following these tables. read & write bus interface timing characteristics with read operation (v cc = 2.4v to 4.5v) item symbol min typ max unit test condition enable cycle time t cyce 1000 ns figures 52 enable pulse width (high level) pw eh 450 and 53 enable rise/fall time t er , t ef 25 address set-up time (rs, r/w to e) t as 60 address hold time t ah 20 data set-up time t dsw 195 data hold time t h 30 read data delay time t ddr 400 ns figure 53 read data hold time t dhr 5 read & write bus interface timing characteristics with read operation (v cc = 4.5v to 5.5v) item symbol min typ max unit test condition enable cycle time t cyce 500 ns figures 52 and 53 enable pulse width (high level) pw eh 230 enable rise/fall time t er , t ef 20 address set-up time (rs, r/w to e) t as 40 address hold time t ah 30 data set-up time t dsw 80 data hold time t h 30 read data delay time t ddr 200 ns figure 53 read data hold time t dhr 5
HD66705U 73 write bus interface timing characteristics without read operation (v cc = 2.4v to 5.5v) item symbol min typ max unit test condition enable cycle time t cyce 500 ns figure 52 enable pulse width v cc = 2.4 to 3.0v p weh 200 (?igh?level) v cc = 3.0 to 5.5v p weh 150 enable rise/fall time t er , t ef 20 address set-up time (rs, r/w to e) t as 60 address hold time t ah 20 data set-up time t dsw 140 data hold time t h 30 clock-synchronized serial interface operation (v cc = 2.4v to 5.5v) item symbol min typ max unit test condition serial clock cycle time t scyc 120 m s figure 54 serial clock high-level width t sch 400 ns serial clock low-level width t scl 400 serial clock rise/fall time t scr , t scf 50 chip select set-up time t csu 60 chip select hold time t ch 200 serial input data set-up time t sisu 200 serial input data hold time t sih 200 reset timing (v cc = 2.4 v to 5.5 v) item symbol min typ max unit test condition reset low-level width t res 10 ms figure 55
HD66705U 74 electrical characteristics notes 1. all voltage values are referred to gnd = 0v. if the lsi is used above the absolute maximum ratings, it may become permanently damaged. using the lsi within the given electrical characteristic is strongly recommended to ensure normal operation. if these electrical characteristic are exceeded, the lsi may malfunction or exhibit poor reliability. 2. v cc > v5 > v ee must be maintained. 3. for die products, specified at 75 c. 4. for die products, specified by the common die shipment specification. 5. the following four circuits are i/o pin configurations except for liquid crystal display output (figure 46). pmos nmos v cc gnd (pull-up mos) nmos pmos v cc pmos v cc gnd (pull-up mos) v cc v cc input enable nmos nmos pmos pmos (input circuit) v cc pmos nmos (tri-state output circuit) output data output enable input enable gnd gnd pmos pins: reset* pins: e/scl, rs/cs*, rw/sda, osc1, im1/0, sft, test opoff pins: db7?b0/id0 figure 46 i/o pin configurations
HD66705U 75 6. the test pin must be grounded. 7. the id5 to id0, im1, im0, sft, exm, and opoff pins must be grounded or connected to v cc . 8. applies to resistor values (rcom) between power supply pins v cc , v1out, v4out, v5out and common signal pins (com1 to com16, coms1, and coms2), and resistor values (rseg) between power supply pins v cc , v2out, v3out, v5out and segment signal pins (seg1 to seg60). 9. this excludes the current flowing through pull-up moss and output drive moss. 10. this excludes the current flowing through the input/output units. the input level must be fixed high or low because through current increases if the cmos input is left floating. 11. the following shows the relationship between the operation frequency (f osc ) and current consumption (i cc ) (figure 47). v cc = 3v 40 30 20 i cc (?) 10 0 0 50 100 150 cr oscillator frequency 200 250 1/10 duty 1/18 duty display on (typ.) sleep (typ.) standby (typ.) v cc = 3v 40 30 20 i ee (?) 10 0 3456 lcd drive voltage : v lcd =v cc - v ee (v) 7 9 10 8 vref=vrefp short-circuited vref?refm short-circuited vref=vrefp=vrerm short-circuited 5.5 15 vref left disconnected 85 figure 47 relationship between the operation frequency and current consumption 12. each com and seg output voltage is within 0.15v of the lcd voltage (v cc , v1, v2, v3, v4, v5) when there is no load. 13. applies to the external clock input (figure 48). oscillator osc1 open osc2 t rcp t fcp th tl 0.7v cc 0.5v cc 0.3v cc duty = th+tl th 100% x figure 48 external clock supply
HD66705U 76 14. applies to the internal oscillator operations using oscillation resistor r f (figure 49). osc1 osc2 r f referential data since the oscillation frequency varies depending on the osc1 and osc2 pin capacitance, the wiring length to these pins should be minimized. 200 150 100 95 50 0 100 200 300 400 500 600 700 800 r f (k ) f osc (khz) v cc =3v (typ.) v cc = 5v (typ.) figure 49 internal oscillation 15. booster characteristics test circuits are shown in figure 50. ( triple boosting ) gnd v cc 1 f 1 f vci c1 c2 v5out2 v5out3 1 f ( double boosting ) gnd v cc 1 f + 1 f vci c1 c2 v5out2 v5out3 + v ee + v ee + + figure 50 booster
HD66705U 77 vup2 = v cc ?v5out2 vup3 = v cc ?v5out3 5.0 4.0 3.0 2.0 4 5 6 7 8 9 10 11 (i) relationship between the obtained voltage and input voltage (ii) relationship between the obtained voltage and temperature vci (v) vup2(v) typ. vci = v cc , fcp =95khz, ta = 25 c 5.0 4.0 3.0 2.0 6 7 8 9 10 11 12 13 14 15 typ. vci = v cc , fcp = 95khz, ta = 25 c vup3(v) vci (v) vci = v cc = 4.5v, r f = 350k , i o = 0.1ma vci = v cc = 2.7v, r f = 300k , i o = 0.1ma double boosting double boosting triple boosting triple boosting ta ( c ) vup2(v) 100 60 20 0 -20 -60 7.5 8.0 8.5 9.0 9.5 typ. ta ( c ) vup3(v) 100 60 20 0 -20 -60 6.5 7.0 7.5 8.0 8.5 typ. referential data (iii) relationship between the obtained voltage and capacitance vci = v cc = 4.5v, r f = 350k , i o = 0.1ma vci = v cc = 2.7v, r f = 300k , i o = 0.1ma 1.5 1.0 0.5 6.0 6.5 7.0 7.5 8.0 typ. c ( f) vup3 (v) double boosting triple boosting c ( f) vup2 (v) 1.5 1.0 0.5 7.0 7.5 8.0 8.5 9.0 typ. figure 50 booster (cont)
HD66705U 78 1.5 2.0 1.0 0.5 0.0 (iv) relationship between the obtained voltage and the load current. i o (ma) vup2 (v) vci = v cc = 4.5v, rf = 350 k ta = 25 c vci = v cc = 2.7v, rf = 300 k ta = 25 c vup3 (v) i o (ma) double boosting triple boosting 1.5 2.0 1.0 0.5 0.0 9.0 8.5 8.0 7.5 7.0 6.5 6.0 typ. typ. 8.0 7.0 6.0 5.0 4.0 3.0 2.0 figure 50 booster (cont) load circuits ac characteristics test load circuits data bus : db0 to db7 test point 50 pf figure 51 load circuit
HD66705U 79 timing characteristics rs r/w e db0 ?db7 vih vil t as t ah pw eh t ef t er t dsw t h valid data t cyce vih vil vil vil t ah vih vil vih vil vil vih vil vih vil figure 52 bus write operation db0 ?db7 rs r/w e pw eh t ah t er t ddr t dhr t cyce v oh1 v ol1 v oh1 v ol1 valid data t as vih vil vih vil vih vih t ah vih vil vil vih vil t ef figure 53 bus read operation
HD66705U 80 cs* scl sda t csu t sch vil t sisu t scr vih vil vih vil vih vil t ch vih vil vih vil t cwl t scf t sih vil t scyc valid data vih start : s end : p valid data figure 54 clock-synchronized serial interface timing reset* vil vil t res figure 55 reset timing
HD66705U 81 cautions 1. hitachi neither warrants nor grants licenses of any rights of hitachi? or any third party? patent, copyright, trademark, or other intellectual property rights for information contained in this document. hitachi bears no responsibility for problems that may arise with third party? rights, including intellectual property rights, in connection with use of the information contained in this document. 2. products and product specifications may be subject to change without notice. confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. hitachi makes every attempt to ensure that its products are of high quality and reliability. however, contact hitachi? sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. design your application so that the product is used within the ranges guaranteed by hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail- safes, so that the equipment incorporating hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the hitachi product. 5. this product is not designed to be radiation resistant. 6. no one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from hitachi. 7. contact hitachi? sales office for any questions regarding this document or hitachi semiconductor products. hitachi, ltd. semiconductor & integrated circuits. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100-0004, japan tel: tokyo (03) 3270-2111 fax: (03) 3270-5109 copyright ?hitachi, ltd., 1998. all rights reserved. printed in japan. hitachi asia pte. ltd. 16 collyer quay #20-00 hitachi tower singapore 049318 tel: 535-2100 fax: 535-1533 url northamerica : http:semiconductor.hitachi.com/ europe : http://www.hitachi-eu.com/hel/ecg asia (singapore) : http://www.has.hitachi.com.sg/grp3/sicd/index.htm asia (taiwan) : http://www.hitachi.com.tw/e/product/sicd_frame.htm asia (hongkong) : http://www.hitachi.com.hk/eng/bo/grp3/index.htm japan : http://www.hitachi.co.jp/sicd/indx.htm hitachi asia ltd. taipei branch office 3f, hung kuo building. no.167, tun-hwa north road, taipei (105) tel: <886> (2) 2718-3666 fax: <886> (2) 2718-8180 hitachi asia (hong kong) ltd. group iii (electronic components) 7/f., north tower, world finance centre, harbour city, canton road, tsim sha tsui, kowloon, hong kong tel: <852> (2) 735 9218 fax: <852> (2) 730 0281 telex: 40815 hitec hx hitachi europe ltd. electronic components group. whitebrook park lower cookham road maidenhead berkshire sl6 8ya, united kingdom tel: <44> (1628) 585000 fax: <44> (1628) 778322 hitachi europe gmbh electronic components group dornacher stra? 3 d-85622 feldkirchen, munich germany tel: <49> (89) 9 9180-0 fax: <49> (89) 9 29 30 00 hitachi semiconductor (america) inc. 179 east tasman drive, san jose,ca 95134 tel: <1> (408) 433-1990 fax: <1>(408) 433-0223 for further information write to:

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